1. Field of the Invention
The present invention relates to a stream processor which comprises an array type processor for implementing a variety of processing, and an information processing apparatus which comprises the stream processor.
2. Description of the Related Art
Recent information processing apparatuses are utilized in increasingly wider applications because their processing capabilities are more improved, and because they are required to have capabilities that provide higher processing performance or process an immense amount of data such as still images and moving images at high speeds.
For satisfying such demands, there has been known an information processing apparatus which comprises, in addition to a host processor, a DSP (Digital Signal Processor) which is dedicated to executing predetermined processing such as processing moving images. However, since the DSP is limited in the kind of processing, the applicant has proposed an array type processor which can be modified by software in the configuration of a data path for executing operational processing. Array type processors are described in Japanese laid-open patent publication No. 2001-312481 (hereinafter called “Patent Document 1”), Japanese laid-open patent publication No. 2003-196246 (hereinafter called “Patent Document 2”), and Non-Patent Document 1 (Hideharu Amano, Akiya Jouraku, Kenichiro Anjo, “A dynamically adaptive switch fabric on a multicontext reconfigurable device,” Proceeding of International Field Programmable Logic and Application Conference, September 2003, p 161-170), and the like.
An array type processor comprises data path unit 105 for executing operational processing, and state management unit 106 for controlling the operation of data path unit 105. Data path unit 105 comprises a plurality of processor elements, and a plurality of switch elements associated therewith, and executes a variety of processing by using software to switch instruction codes supplied to each processor element and to each switch element. FIG. 1 illustrates an information processing apparatus disclosed in Patent Document 2. The information processing apparatus illustrated in FIG. 1 has MPU 101, stream processor 102 which comprises array type processor 104, and input/output control circuit 107 for controlling input/output of data to/from array type processor 104; memory 103 for temporarily storing data supplied to or delivered from stream processor 102; and bus 108 for interconnecting stream processor 102 and memory 103. Stream processor 104 can execute a plurality of processing sessions in parallel if it is provided with a plurality of array type processors 104.
The array type processor fundamentally differs from a CPU, a DSP and the like in structure and operation. To have the array type processor execute certain types of processing, the type of the processing needs to be specified before the data that is to be processed is sent to the array type processor, and the array type processor needs to have been set in a state before it can execute the processing. In other words, there is a problem with the array type processor in that a certain period of time is required until it is ready to execute processing after the type of processing has been specified, so that data processing efficiency is accordingly reduced.
For example, in the array type processor illustrated in FIG. 1, the data path unit first receives a command for specifying processing from the input/output control circuit. The command is decoded to generate an event which is then transferred to the state management unit. The state management unit returns to the data path unit an instruction pointer (indicative of an instruction code address at which an associated instruction code is stored) that corresponds to the event transferred from the data path unit. The data path unit switches the states of the processor element and switch element, respectively, in accordance with the instruction code specified by the instruction pointer (state transition). Then, the data path unit receives data to be processed from the input/output control circuit to start the specified processing after the state transition has been completed. In this way, the array type processor shown in FIG. 1 requires a long time before it starts processing data applied thereto because the array type processor analyzes the type of command in the data path unit, and transitions to a state in which it can execute processing specified by the command under control of the state management unit.
On the other hand, the aforementioned Non-Patent Document 1 shows an example which implements a four-input/four-output cross-bar switch using an array type processor. As illustrated in FIG. 2, Non-Patent Document 1 describes a state transition diagram, as an operation of a cross-bar switch, which shows that the array type processor transitions from initial state FC to state 00 among states 00/10/20/30, again transitions to state 01, 02 or 03, and returns to initial state FC after processing is terminated. Non-Patent Document 1 clearly states that a latency of several cycles is needed until a desired circuit is started after the array type processor determines a condition for transitioning to the next state.
There are a variety of types of processing which can be executed by array type processors. For example, other data can be read from memory during processing, and processing can be continued using the read data.
While an array type processor comprises a built-in memory, its memory capacity is often limited. Therefore, in processing that is executed by the array type processor, when reference is needed, in the middle of processing, to a table or data which requires a large storage capacity, access must be made to a memory which stores them. This memory corresponds, for example, to memory 103 shown in FIG. 1. To access memory from the array type processor, the array type processor may issue a command and an address for reading/writing data and transmit write data when the data is to be written, or it may receive read data retrieved from the memory when the data is read.
For example, when the array type processor execute processing session A and processing session B and processing session A is divided into processing sub-sessions A-a, A-b, A-c that correspond to accesses made to a memory in order to execute processing session A, as illustrated in FIG. 3, the array type processor, upon receipt of data, determines the type of the data, i.e., whether the data is intended for processing session A or processing session B. Then, determining that the data is intended for processing session A, the array type processor executes processing sub-session A-a for the data, accesses the memory to read data for use in the next processing sub-session A-b upon termination of processing sub-session A-a, and executes processing sub-session A-b together with data that results from processing sub-session A-a. When processing sub-session A-b is terminated, the array type processor again accesses memory to read data for use in the next processing sub-session A-c, and executes processing sub-session A-c together with data that results from processing sub-session A-b. Finally, when processing sub-session A-c is terminated, the array type processor accesses memory to write data that results from processing sub-session A-c, and returns to state of a determination of data type.
Here, in the conventional array type processor, when the array type processor issues a read address (issuance of the memory address) to the memory for reading data upon termination of processing sub-session A-a and processing sub-session A-b, the array type processor interrupts the operation (for waiting for data from the memory) until it receives data read from the memory (reception of memory data). Consequently, this interruption of the operation also causes a lower processing efficiency of the array type processor.